1. Field of the Invention
The present invention relates to design for test improvements, and specifically to a method and apparatus for fault tolerant and flexible test signature generator within an integrated device.
2. Description of the Related Art
Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as a manufacturing defect may prevent the IC from performing all of the functions that an IC is designed to perform. Such demands require verification of the design of the IC and also various types of electrical testing after the IC is manufactured.
However, as the complexity of the IC increases, so does the cost and complexity of verifying and electrically testing each of the devices in the IC. Electrical testing ensures that each node in a VLSI circuit functions properly. Therefore, each node needs to individually, and in conjunction with the other node in the IC, function properly in all possible combinations of operations. Typically, electrical testing is performed by automated testing equipment (ATE) that employs test vectors to perform the desired tests. A test vector describes the desired test input (or signals), associated clock pulse (or pulses), and expected test output (or signals) for every package pin during a period of time, often in an attempt to xe2x80x9ctestxe2x80x9d a particular node. For complex circuitry, this may involve a large number of test vectors and, accordingly, a long test time.
One way to address this problem is through design for test (DFT). DFT methods utilize various test circuits. One type of test circuit is a scan path or a scan loop in the logic circuit. A scan path or scan loop comprises of a chain of synchronously clocked master/slave latches (or scan flip flops), each of which is connected to a particular node in the logic circuit. Typical scan circuit designs involve one or more separate scan paths or scan loops. The scan latches can be loaded with a serial data stream of scan vectors that set the logic circuit nodes to a predetermined state. The logic circuit then can be operated in normal fashion and the result of the operation is stored in its respective latch. A scan out operation serially unloads the contents of the latches and the result of the test operation at the associated nodes is analyzed for improper node operation.
A typical circuit for verifying functionality of the nodes is utilizing a single multiple input signature register (MISR) to receive the outputs of scan chains. Also, additional logic is needed for initializing the integrated device to prevent signature corruption due to un-initialized nodes. However, this requires significant simulation and cost overhead due to the additional logic and design simulation to insure all the nodes are initialized. Also, any scan chain defect adversely impacts the data and signature corruption within the MISR.